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Jia Wang, Ph.D.

Associate Professor

Office: 

3301 South Dearborn, Siegel Hall 317

Phone: 

312.567.3696

Fax: 

312.567.8976

Email: 

Education 

Ph.D., EECS, Northwestern University, 2008
M.S., ECE, Northwestern University, 2005
B.S., EE, Tsinghua University, 2002

Expertise 

VLSI design automation, including sequential optimization, floorplanning, and design for manufacturability; synthesis for embedded systems and distributed systems; and algorithm design.

Research 

Dr. Wang joined the Department of Electrical and Computer Engineering in 2008. His research interests include VLSI design automation, e.g., sequential optimization, floorplanning, and design for manufacturability; synthesis for embedded systems and distributed systems; and algorithm design.

Publications 

Z. Gu, Jia Wang, R. P. Dick, and H. Zhou, Incremental Exploration of  the Combined Physical and Behavioral Design Space. ACM/IEEE Design Automation Conference, Anaheim, CA, 2005.

C. Lin, Jia Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.

Jia Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound. ACM/IEEE Design Automation Conference, San Francisco, CA, 2006.

Jia Wang, D. Das, and H. Zhou, Gate Sizing by Lagrangian Relaxation Revisited. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.

Jia Wang and H. Zhou. An Efficient Incremental Algorithm for Min-Area Retiming. ACM/IEEE Design Automation Conference, Anaheim, CA, 2008.

Jia Wang and H. Zhou. Linear Constraint Graph for Floorplan Optimization with Soft Blocks. To appear, IEEE/ACM International Conference on Computer-Aided Design, 2008.