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ECE Research Seminar Series

Event Date 

October 11, 2019 - 12:45pm to 1:45pm

Location 

Illinois Tech
Siegel Hall Auditorium
3301 S. Dearborn
Chicago, IL 60616

Description 

Please join the ECE Department as we welcome guest speaker Nandakishor Yadav to present at our Research Seminar.  Dr. Yadav's will speak on his research, "Stable and Reliable SRAM Circuit Design: A Device/Circuit Co-Design Approach."

Abstract

Reliability of electronic components such as a semiconductor memory is defined in terms of the mean time between failures (MTBF). Temperature variations and operating conditions have a substantial effect on the MTBF of individual components as well as the overall performance of the system. Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent bias temperature instability (NBTI and PBTI both) degradation, time-dependent dielectric breakdown (TDDB), hot-carrier injection (HCI) and high energy partial trapping induced random telegraph noise (RTN). Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of MOS transistors increases with time under NBTI and PBTI. To fundamentally improve reliability, the design should be focused on improving the robustness of the basic functions of circuit or process and apply device/circuit design methods to optimize the basic functions approach under real conditions. These robust design activities should be conducted by taking into consideration the physics of individual transistor, operating conditions, circuit board layout, and power requirements. In this work, we proposed a stable, high performance and reliable SRAM using the device circuit co-design approach. First, we proposed a reliable FinFET device design technique, dual-k gate insulator, and symmetric spacer are used to improve the reliability and performance, respectively of the FinFET.

An on-chip adaptive body bias (O-ABB) circuit to compensate for the degradation due to NBTI aging is presented. The proposed sensor provides a high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement.

Biography

Dr. Yadav is a Senior Research Fellow/Visiting Research Scholar at Electrical and Computer Engineering Illinois Institute of Technology, Chicago. He received his Ph.D. in Process Variation Aware SRAM design from Indian Institute of Information Technology and Management, Gwalior, India (An autonomous institute of the department of MHRD, Govt. of India) in 2015. He has worked as a post-doctoral fellow at Indian Institute of Technology Indore, India (An autonomous institute of the department of MHRD, Govt. of India). He also worked as an assistant professor at Department of Electronics and Communication Engineering, Amity University Noida, India.

Dr. Yadav has also received one research project from the Science and Engineering Research Board, India and it successfully completed in 2018. He has authored/co-authored of more than 15 research papers in peer-reviewed international journals (3 in IEEE Transactions) and 16 in international conferences.

If you have any questions about the seminar, please contact Prof. Ken Choi in ECE (7-3461, kchoi12@iit.edu).